Tutorials

Abstract
Recently, the semiconductor industry and academia are facing limitations of existing computing system as the development of device scaling and process integration slows down. From this trend, new computing systems such as in-memory computing and neuro-inspired computing are emerging, and their applications to new fields are also expanding. In this presentation, we will first look into what is required for the implementation of memory-based high-density and low-power hardware neural system, and introduce the recent research achievements so far.

Abstract
With the increasing data rate to 112Gb/s per lane, PAM-4 with ADC-based RX has become the most commonly employed modulation for ultra-high-speed serial links. To keep the data-rate increasing beyond 200Gb/s/lane, modulation techniques exhibiting high bandwidth efficiency have been investigated for multiple reasons, such as reduced attenuation and lower required DAC/ADC conversion rate. With a particular emphasis on orthogonal frequency division multiplexing (OFDM), this talk covers link modeling with OFDM, design-space exploration, and implementation challenges for enabling a data rate of 200Gb/s and beyond in wireline transceivers.

Abstract
Machine learning and artificial intelligence technology are playing the key role in the 4th industrial revolution and tremendous amount of researches are actively conducted to blend the technologies into our daily lives with practical applications such as autonomous vehicles/robots/drones, AI speaker, smart surveillance, etc. Most of current works rely on GPU that is not a practical solution to embedded systems and mobile platforms due to its large form factor and power consumption. Instead, low-power hardware accelerators are essential for feasible implementation and they have been investigated recently with different aspects and architectures. In this talk, I will review the technological challenges and trends in latest AI accelerators as well as introducing practical systems on AI applications.

Abstract
This talk presents the design, implementation, and validation of a wireless neural implant that uses body-coupled power delivery and data transmission, considering closed-loop multichannel wireless neural interfaces. The scheme is applicable to a central nervous system based on: 1) its use of bidirectional communications combined with wireless reception without recourse to customized and dedicated antennas or transducers and 2) its exploitation of an undemanding electrode interface and the conductive properties of the body. From the details of body-coupled channel characteristics, the implementation of the power receiver and data transceivers to the prototyped system using integrated circuits are introduced, demonstrating its feasibility in miniaturized wireless neural implant applications.

Abstract
Eye pupil tracking is important for augmented reality (AR) three-dimensional (3D) head-up displays (HUDs). Accurate and fast eye tracking is still challenging due to multiple driving conditions with eye occlusions, such as wearing sunglasses. We presents a AR 3D HUD system for commercial use that can handle practical driving conditions. Our system classifies human faces into bare faces and sunglasses faces, which are treated differently. Experiments show that our method achieves high accuracy and speed, approximately 1.5 and 6.5 mm error for bare and sunglasses faces, respectively, at less than 10 ms on a 2.0GHz CPU. The proposed method, combined with AR 3D HUDs, shows promising results for commercialization with low crosstalk 3D images.

Abstract
When we design an SoC or a multi-die IC consisting of 3rd-party IPs, heterogeneous components, or functional dice, synchronization of the clock signals across all of them could be a headache. Fortunately, Delay-Locked Loop (DLL) comes to the rescue. However, a DLL is traditionally built with some analog circuitry inside and thus making the design process complicated if not mysterious for system integrators. The emergence of cell-based DLL design style over the past two decades has alleviated this problem greatly. A cell-based DLL design is not only small, but also robust to the process and temperature variation. Also, it could lend itself to automation as a DLL compiler and so one can generate a DLL instance on the push of a button.
In this tutorial, we will take on a step-by-step journey to show you how to make your own robust and testable fault-tolerant DLL using only standard cells. In the first part, specific topics for the design of a basic DLL such as phase detector, tunable delay line, phase-locking procedure will be briefly reviewed. In the second part, Fault and soft-Error Tolerant (FET) DLL architecture, featuring static timing correction and dynamic timing correction schemes to keep the phase error small while withstanding the attack of run-time faults or soft errors. Finally in the third part, we will touch upon the online DLL monitoring schemes which are often necessary to make a FET DLL truly trustworthy throughout its entire lifecycle.

Abstract
A space-induced crisis is recognized as the cause of trouble that Moore’s Law is currently facing. The contemporary practice of this empirical law is considered as happening within a space-dominant paradigm. An alternative of exploiting potential in the dimension of time is identified as an emerging paradigm in microelectronics. The new practice is termed a time-oriented paradigm. It is justified as the turn of Moore’s Law from space to time. The resultant Time-Moore strategy is envisioned as the next-generation enabler for continuing Moore’s Law’s pursuit of everhigher information processing power and efficiency. It also serves as the perpetuation of the spirit that Moore’s law is nothing but a collective storied history of innovations. In the first part of this tutorial, by following Thomas Kuhn’s seminal work around the concepts of paradigm and scientific revolution, the argument for the Time-Moore strategy (Time-Moore: to use time more) and the paradigm shift from space to time is carried out through philosophical persuasion rather than technical proof due to the difficult challenge of change-of-mindset. The second part provides solid technical materials for supporting this transition from the old paradigm to the new one. The goal of this tutorial is to reevaluate the contemporary practice of microelectronics, identify the cause of the current crisis, advocate a change-of-mindset to circumvent the crisis, and ultimately point out a new route for advancing. After achieving so many unprecedented accomplishments through several decades of relentless endeavor, it’s time for the big ship of Moore’s Law to make a turn.

Abstract
Deep learning algorithms gathered serious attention due to their outstanding performance in various tasks. Their application areas are fast expanding from computer vision and speech recognition to multi-modal understanding. While power-saving techniques such as quantization, network compression, and pruning have been successfully adopted in pre-trained models, they often become next to useless when applied to the training process. This talk will discuss various algorithmic and hardware optimization techniques enabling energy-efficient training processors.