Special Session #1
Design and Testing Techniques for Computing-In-Memories
Organizer: Prof. Yu-Guang Chen (National Central University, Taiwan)
Abstract
Computing-In-Memories is a promising approach to overcome Von Neumann Bottleneck in computer system when running data-intensive applications. By slightly modifying the structure and peripheral circuits, the logic and arithmetic computations can be done directly in the memory, which significantly improves the performance. Various Computing-In-Memory architectures as well as operation techniques have been addressed recently for various applications, especially neural network computations. However, the CIM suffers from threats of reliability issues due to the vulnerable essence. Therefore, it is important to provide appropriate testing and tolerance techniques. In this session, four papers will discuss the designing and testing techniques for Computing-In-Memories. The first paper provides a brief tutorial on computing-in-memory (CIM) designs and test techniques, and the second paper propose a novel higher precision dot multiplication engine for MAC operations. The third paper gives an aging-aware in-memory computing framework to tolerance aging-induced reliability degradation, while the fourth paper shows a synaptic array and weight mapping method for DNNs.
Computing-In-Memories is a promising approach to overcome Von Neumann Bottleneck in computer system when running data-intensive applications. By slightly modifying the structure and peripheral circuits, the logic and arithmetic computations can be done directly in the memory, which significantly improves the performance. Various Computing-In-Memory architectures as well as operation techniques have been addressed recently for various applications, especially neural network computations. However, the CIM suffers from threats of reliability issues due to the vulnerable essence. Therefore, it is important to provide appropriate testing and tolerance techniques. In this session, four papers will discuss the designing and testing techniques for Computing-In-Memories. The first paper provides a brief tutorial on computing-in-memory (CIM) designs and test techniques, and the second paper propose a novel higher precision dot multiplication engine for MAC operations. The third paper gives an aging-aware in-memory computing framework to tolerance aging-induced reliability degradation, while the fourth paper shows a synaptic array and weight mapping method for DNNs.
Special Session #2
Memory-Centric Accelerator Design for Deep Neural Network Applications
Organizers: Prof. Po-Tsang Huang (National Yang Ming Chiao Tung University, Taiwan)
Prof. Yung Du (Nanjing University, China)
Abstract
Deep neural networks (DNN) are widely used in feature classification, object detection, recommender system and so on. Moreover, graph neural networks (GNNs) appear to be a powerful approach to analyzing non-Euclidean data structures and achieving unprecedented performance on graph processing tasks. Unfortueately, DNNs and GNNs are both memory-intensive and computation-intensive, and data accesses and movements dominate the overall energy efficiency by matrix computations and ff-chip memory accesses. In this special session, therefore, memory-centric computing and accelerator design will be discussed to reduce off-chip memory accesses from the aspects of algorithms, architectures, and circuits, particularly emphasizing on the design techniques of data reuse, workload mapping, dataflow, and computation-in-memory circuits.
Deep neural networks (DNN) are widely used in feature classification, object detection, recommender system and so on. Moreover, graph neural networks (GNNs) appear to be a powerful approach to analyzing non-Euclidean data structures and achieving unprecedented performance on graph processing tasks. Unfortueately, DNNs and GNNs are both memory-intensive and computation-intensive, and data accesses and movements dominate the overall energy efficiency by matrix computations and ff-chip memory accesses. In this special session, therefore, memory-centric computing and accelerator design will be discussed to reduce off-chip memory accesses from the aspects of algorithms, architectures, and circuits, particularly emphasizing on the design techniques of data reuse, workload mapping, dataflow, and computation-in-memory circuits.
Special Session #3
Algorithm-or Architecture-Level Schemes for Reducing Operation Complexity of Neural Networks
Organizers: Prof. Xin Lou (SanghaiTech University, China)
Prof. Song-Nien Tang (Chung Yuan Christian University, Taiwan)
Abstract
Recently, neural network schemes based on deep learning technology have been widely used in many fields for artificial intelligence (AI) applications. To increase the execution speed of edge AI devices, it has become a trend that the hardware acceleration schemes have been applied to the neural network inference implementation. In such a development, the reduction of hardware costs and power consumption is an important issue. For this issue, the simplification of neural network inference operations is an effective approach and both algorithmic and hardware architectural solutions can be considered. In this proposal, we plan to explore and propose suitable schemes in the algorithm or architecture level aiming to reduce the operation complexity of neural networks. We expect the proposed works lend support to area- and energy-efficiency improvements in the hardware acceleration design for the neural network inference implementation.
Recently, neural network schemes based on deep learning technology have been widely used in many fields for artificial intelligence (AI) applications. To increase the execution speed of edge AI devices, it has become a trend that the hardware acceleration schemes have been applied to the neural network inference implementation. In such a development, the reduction of hardware costs and power consumption is an important issue. For this issue, the simplification of neural network inference operations is an effective approach and both algorithmic and hardware architectural solutions can be considered. In this proposal, we plan to explore and propose suitable schemes in the algorithm or architecture level aiming to reduce the operation complexity of neural networks. We expect the proposed works lend support to area- and energy-efficiency improvements in the hardware acceleration design for the neural network inference implementation.
Special Session #4
Design, Analysis and Tools for Integrated Circuits and Systems (DATICS)
Organizer: Prof. Ka Lok Man (Xi’an Jiaotong-Liverpool Unversity, China)
Abstract
DATICS workshops/special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC’22 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade.
The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC’22 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences.
DATICS workshops/special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC’22 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade.
The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC’22 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences.
Special Session #5
Emerging Applications and FPGA Implementation of Machine Learning
Organizers: Prof. Hiroyuki Tomiyama (Ritsumeikan University, Japan)
Prof. Hiroki Nishikawa (Osaka University, Japan)
Abstract
Artificial intelligence based on machine learning is now a fundamental part of the social infrastructure that supports our daily lives, and the application fields of machine learning are rapidly expanding. Machine learning is a general-purpose technology, but optimizing internal structures and algorithms for each application is necessary to achieve high inference accuracy. Furthermore, in order to reduce learning or inference time while keeping a high degree of flexibility and scalability, FPGA implementation, rather than CPUs or GPUs, is more effective.
This special session invites six papers on emerging applications and FPGA implementation of machine learning. The first five papers describe machine learning technologies for emerging applications such as energy management, autonomous drones, abnormal event detection, spy photography prevention and human detection. The last paper presents an efficient FPGA implementation of machine learning.
Artificial intelligence based on machine learning is now a fundamental part of the social infrastructure that supports our daily lives, and the application fields of machine learning are rapidly expanding. Machine learning is a general-purpose technology, but optimizing internal structures and algorithms for each application is necessary to achieve high inference accuracy. Furthermore, in order to reduce learning or inference time while keeping a high degree of flexibility and scalability, FPGA implementation, rather than CPUs or GPUs, is more effective.
This special session invites six papers on emerging applications and FPGA implementation of machine learning. The first five papers describe machine learning technologies for emerging applications such as energy management, autonomous drones, abnormal event detection, spy photography prevention and human detection. The last paper presents an efficient FPGA implementation of machine learning.
Special Session #6
Hardware Security, Reliability and Trust for SoCs
Organizers: Dr. Zhao Huang (Xidian University, China)
Dr. MD Tanvir Arafin (George Mason University, USA)
Abstract
System-on-Chip (SoC) chip is the important component of social and personal information systems, which has currently dominated in the end-application market. However, with the development of modern SoC technology and the ubiquity of SoC-based computing devices connected via network, the security, reliability and trust of SoCs have become a pressing issue during the past decade. Since the end product of SoC requires the cooperation from third-party (3P) intellectual property (IP) core vendors, commercial electronic design automation (EDA) companies and offshore foundries, any part of this global business model can be an entry point for hackers to launch various attacks. For example, an adversary may insert Hardware Trojan (HT) into SoC/IP design, develop SoCs using untrusted EDA tools, malicious integrate untrusted 3PIP, overbuild SoC chips, etc. All of these hardware-based issues will significantly affect the security, reliability and trust of SoC chips. Given this situation, it is both critical and challenging to study defensive strategies to alleviate these potential security threats.
In this Special Session (SS), we will have discussions on the security, reliability and trust of SoCs from various viewpoints. Formal verification, Model Checking, Evolvable Hardware, Reinforcement Learning, optimized SM4 and EDA Tool security are discussed for exploring research directions of secure SoCs.
System-on-Chip (SoC) chip is the important component of social and personal information systems, which has currently dominated in the end-application market. However, with the development of modern SoC technology and the ubiquity of SoC-based computing devices connected via network, the security, reliability and trust of SoCs have become a pressing issue during the past decade. Since the end product of SoC requires the cooperation from third-party (3P) intellectual property (IP) core vendors, commercial electronic design automation (EDA) companies and offshore foundries, any part of this global business model can be an entry point for hackers to launch various attacks. For example, an adversary may insert Hardware Trojan (HT) into SoC/IP design, develop SoCs using untrusted EDA tools, malicious integrate untrusted 3PIP, overbuild SoC chips, etc. All of these hardware-based issues will significantly affect the security, reliability and trust of SoC chips. Given this situation, it is both critical and challenging to study defensive strategies to alleviate these potential security threats.
In this Special Session (SS), we will have discussions on the security, reliability and trust of SoCs from various viewpoints. Formal verification, Model Checking, Evolvable Hardware, Reinforcement Learning, optimized SM4 and EDA Tool security are discussed for exploring research directions of secure SoCs.
Special Session #7
Analysis and Design of Power and Energy Circuits and Systems
Organizer: Prof. Hiroo Sekiya (Chiba University, Japan)
Abstract
This session discusses analysis and design of power and energy circuits and systems. The topics of dc-dc converters, wireless power transfer, energy-harvesting circuits, and gate drivers are included in this proposed session. Power energy circuits and systems are becoming increasingly important as awareness of environmental issues grows. The dc-dc converters are required high frequency, small and light scale, and high efficiency. The energy-harvesting and wireless-power-transfer systems are also done, which are now at the stage of looking at practical applications. Because of the high-frequency trend, the gate-driver design is one of the most important issues. This session can discuss the cutting-edge research results around the above problems.
This session discusses analysis and design of power and energy circuits and systems. The topics of dc-dc converters, wireless power transfer, energy-harvesting circuits, and gate drivers are included in this proposed session. Power energy circuits and systems are becoming increasingly important as awareness of environmental issues grows. The dc-dc converters are required high frequency, small and light scale, and high efficiency. The energy-harvesting and wireless-power-transfer systems are also done, which are now at the stage of looking at practical applications. Because of the high-frequency trend, the gate-driver design is one of the most important issues. This session can discuss the cutting-edge research results around the above problems.
Special Session #8
Emerging Applications of Intelligent System Semiconductor
Organizer: Prof. Suk-Ju Kang (Sogang University, Korea)
Abstract
In this special session, papers on variously applicable systems, circuit designs, and device technologies related to intelligent semiconductors will be presented. Through these papers, we will look at recent technology trends and research directions, and discuss them from various research perspectives.
In this special session, papers on variously applicable systems, circuit designs, and device technologies related to intelligent semiconductors will be presented. Through these papers, we will look at recent technology trends and research directions, and discuss them from various research perspectives.
Special Session #9
Low Power Accelerator Design Utilizing Neural Networks for IoT Applications
Organizer: Prof. Tony Tae-Hyoung Kim (Nanyang Technological University, Singapore)
Abstract
Recent development of Artificial Intelligence (AI) and Machine Learning (ML) have driven the progress in accelerator design based on neural networks. While deep neural networks (DNNs) have demonstrated substantial advantages in various domains, small-scale neural networks have also attracted research interest because of edge computing where energy efficiency and hardware complexity are significant design constraints. In this special session, various low power accelerators for edge computing based on neural networks will be presented. Several accelerators with different architectures and target applications will be discussed to address the limitations of DNNs for edge computing or IoT applications.
Recent development of Artificial Intelligence (AI) and Machine Learning (ML) have driven the progress in accelerator design based on neural networks. While deep neural networks (DNNs) have demonstrated substantial advantages in various domains, small-scale neural networks have also attracted research interest because of edge computing where energy efficiency and hardware complexity are significant design constraints. In this special session, various low power accelerators for edge computing based on neural networks will be presented. Several accelerators with different architectures and target applications will be discussed to address the limitations of DNNs for edge computing or IoT applications.
Special Session #10
Emerging techniques for neural networks, non-linear, and bio-related circuits and systems
Organizers: Prof. Kyeong-Sik Min (Kookmin University, Korea)
Prof. Fernando Corinto (Politecnico di Torino, Italy)
Abstract
In this special session, emerging techniques of neuromorphic, neural networks, non-linear circuits, sensing, etc. are discussed and presented. Based on emerging devices such as memristors, etc., potential hardware solutions are presented for implementing neuromorphic and neural network systems. In addition, line resistance problem that can affect the performance and energy consumption of emerging device based circuits is explained and reviewed. For deep understanding of brain-mimicking circuits, chaotic property of non-linear circuits is shared and discussed at the session. And, a new sensing technique for drones flying at night is presented and explained for future application of next-generation AI based mobility.
In this special session, emerging techniques of neuromorphic, neural networks, non-linear circuits, sensing, etc. are discussed and presented. Based on emerging devices such as memristors, etc., potential hardware solutions are presented for implementing neuromorphic and neural network systems. In addition, line resistance problem that can affect the performance and energy consumption of emerging device based circuits is explained and reviewed. For deep understanding of brain-mimicking circuits, chaotic property of non-linear circuits is shared and discussed at the session. And, a new sensing technique for drones flying at night is presented and explained for future application of next-generation AI based mobility.
Special Session #11
Circuits and Systems of Artificial Intelligence and Security
Organizer: Prof. Hanho Lee (Inha University, Korea)
Abstract
Artificial intelligence (AI) and security are playing an increasingly crucial role in the IoT, 5G/6G, and autonomous mobility applications, and they have also become the fundamental components of modern intelligent society. The applications of AI and security for IoT, 5G/6G and autonomous mobility need to be portable, lightweight, low-latency and high-speed to provide reliable service. Meanwhile, massive devices connected to the edge of communication networks should be post-quantum safe and secure, because emerging quantum computers can easily crack the traditional public-key ciphers. To meet the requirements of high-throughput and diverse application scenarios of next-generation communications and autonomous mobility, it is necessary to resort to configurable and low-latency algorithms and architectures of AI and post-quantum cryptography. The high-performance, low-latency domain specific architecture has become a trend of circuits and systems design in the post-Moore era, which can also be applied to the AI and security in a wide range of applications.
Artificial intelligence (AI) and security are playing an increasingly crucial role in the IoT, 5G/6G, and autonomous mobility applications, and they have also become the fundamental components of modern intelligent society. The applications of AI and security for IoT, 5G/6G and autonomous mobility need to be portable, lightweight, low-latency and high-speed to provide reliable service. Meanwhile, massive devices connected to the edge of communication networks should be post-quantum safe and secure, because emerging quantum computers can easily crack the traditional public-key ciphers. To meet the requirements of high-throughput and diverse application scenarios of next-generation communications and autonomous mobility, it is necessary to resort to configurable and low-latency algorithms and architectures of AI and post-quantum cryptography. The high-performance, low-latency domain specific architecture has become a trend of circuits and systems design in the post-Moore era, which can also be applied to the AI and security in a wide range of applications.
Special Session #12
Simulation and Analysis for Nonlinear Problems
Organizer: Prof. Yoko Uwate (Tokushima University, Japan)
Abstract
The systems that exist in the real world are very high-dimensional and complex, and the most of them are nonlinear systems. Therefore, the simulation and analysis of nonlinear systems are very important for the future development of engineering applications, especially in the field of SoC.
This special session will present and discuss the following research topics; optimization using chaotic dynamics and bifurcation, auditory models focusing on nonlinear features, and time series classification using neural networks with nonlinear techniques.
The systems that exist in the real world are very high-dimensional and complex, and the most of them are nonlinear systems. Therefore, the simulation and analysis of nonlinear systems are very important for the future development of engineering applications, especially in the field of SoC.
This special session will present and discuss the following research topics; optimization using chaotic dynamics and bifurcation, auditory models focusing on nonlinear features, and time series classification using neural networks with nonlinear techniques.
Special Session #13
Design and Analysis of Nonlinear Circuits and Networks
Organizer: Prof. Yoshifumi Nishio (Tokushima University, Japan)
Abstract
In recent years, nonlinear circuits and networks become more and more important, because intelligent and flexible systems for future electronic systems require complex nonlinear circuits and networks. From the beginning of the 20th century, plenty of design and analysis methods for nonlinear circuits and networks have been developed over 100 years. However, we need more powerful tools to design low cost power electronic circuits, to analyze large scale complex nonlinear networks, and to realize more intelligent artificial neural networks.
In this special session, 5 papers are invited to show examples of recent works on design and analysis of such nonlinear circuits and networks.
In recent years, nonlinear circuits and networks become more and more important, because intelligent and flexible systems for future electronic systems require complex nonlinear circuits and networks. From the beginning of the 20th century, plenty of design and analysis methods for nonlinear circuits and networks have been developed over 100 years. However, we need more powerful tools to design low cost power electronic circuits, to analyze large scale complex nonlinear networks, and to realize more intelligent artificial neural networks.
In this special session, 5 papers are invited to show examples of recent works on design and analysis of such nonlinear circuits and networks.